1. Field of the Invention
The present invention concerns computer systems in which pluggable units have to be inserted or extracted when the system is powered on. The invention particulary relates to a method and a system which allow the replacement or addition of such a unit without also requiring the system to be powered down thereby avoiding signal disturbances on a system bus of the computer system caused by that live insertion.
2. Description of the Related Art
Various apparatus and methods for the rapid interconnection of electrical circuits, such as peripheral device interfaces or control circuits to computer busses, are known in the art. In an effort to minimize the impact of plugging into a digital bus, the normal procedure has been to shut down or disable the bus so that new devices would not disrupt data flow on the bus. Hereby particular control circuits are utilized which usually contain a voltage regulator. Circuit interconnections to the bus and for power and data transfer are accomplished via edge connectors. The edge connectors are mounted on a printed circuit board which is plugged into a corresponding receptacle for connection to the bus. Plugging in the board establishes electrical contact between the edge connectors and the corresponding bus receptacle and thus both provides power to the electronic components on the board and interconnects it with the bus in one operation. For hot plugging, the common method of interconnection is to increase the length of at least the ground contact on the edge connector, so that a ground contact can be completed prior to the electrical connection of the other contacts for the application of power and the transfer of data signals.
Another concept for controlled insertion and removal of circuit modules which are interconnected by a bus is known from U.S. Pat. No. 4,835,737. According to the teaching of that reference, the operation of the bus is inhibited during the period a module is being inserted into a connector connected to the bus, and the bus is reactivated after the module has been inserted. When the module is to be inserted in an associated connector, a switch on the module is operated to provide an inhibit signal via the associated connector to a control circuit which inhibits operation of the bus. Upon full insertion of the module in the associated connector, the switch is operated to a second state in which the inhibit signal to the control circuit is reactivated. As a consequence, the control circuit again enables the bus to perform normal operations. However, quiescing of the bus during the insertion period has serious disadvantages, since there is no graceful way to manage peripherals or input/output (I/O) devices during the quiesce interruption.
A further approach is disclosed in U.S. Pat. No. 5,310,998 "Method and System for Placing a Bus on Hold During the Insertion/Extraction of an IC Card Into/From a Computer" assigned to Toshiba Corporation, which is particulary related to portable computers where a host IC card has to be inserted/extracted during operation of the computer. In such computer systems, when an IC card is extracted from an IC card holder, commonly a door has to be opened. A detection signal is output from a detecting circuit to a bus controller by detecting opening of the door. Upon receiving the detection signal, a hold request signal is output from the bus controller to a Central Processing Unit (CPU). In response to the hold request signal, a hold acknowledge signal is output from the CPU to the bus controller after the computer process to be executed is completed. A buffer control signal for disabling a buffer is output from the bus controller by receiving the hold acknowledge signal, thereby interrupting an access signal from the CPU, to hold a bus. As a disadvantage of that approach, there are no provisions which avoid bus disturbances of these signals which adversely affect the system, but allow further managing of peripherals during the live insertion procedure. Beyond that, the approach is not generally applicable to other live insertion systems. For example, it defines use of a door being opened or closed to indicate the progress of live insertion to the system. It requires the use of a buffer to isolate the CPU from the bus where live insertion occurs.
A further mechanism which provides the ability to quiesce a system bus in order to protect it against system malfunction is disclosed in IBM Technical Disclosure Bulletin Vol. 35, No. 5, October 1992, pp. 391-394, and entitled "Method for Card Hot Plug Detection and Control". The proposed method serves to control system bus signal disruptions that may occur as a result of card hot plugging. A receiver circuit on each card detects when a card has been inserted and causes the system bus to be quiesced. When the card has been fully inserted, powered-on, and is otherwise ready for system bus operation, the system bus is allowed to run. When card removal is detected via a service bus, the system bus can again be quiesced.
From IBM Technical Disclosure Bulletin, Volume 29, No.7, December 1986, page 2877, a circuitry is known for allowing a data cartridge to be hot plugged into an operating terminal without disrupting terminal operation. Other circuits are included in this circuitry to isolate the cartridge connector from the address, data and control busses to which it is logically connected. The buffer circuits are interposed between the cartridge connector and the busses to avoid bus noise. The buffer is kept in a high impedance state unless the presence of the cartridge has been indicated by an interrupt signal provided directly to a microprocessor.
An improved hot pluggable circuit is further disclosed in U.S. Pat. No. 5,432,916 entitled "Precharge for Non-Disruptive Bus Live Insertion" which is assigned to IBM Corporation. That reference describes hot plugging of an electrical circuit into a separate non-quiesced signal network in an active system, such as a digital or an analog bus. The inventive concept proposed is the addition of a preconditioning network to precondition the electrical circuit to be hot plugged by partially precharging the parasitic input capacitances of the electrical circuit before hot plugging. The precharging of the parasitic input capacitances serves to minimize electrical transient effects on the active system. According to that approach each pluggable unit is precharged; the bus itself is not preconditioned.
When an electrical circuit such as a printed circuit board is inserted live into a signal network of an analog or digital system, the active system's signal voltage may be high, low, or a transition between these two states. No knowledge of the exact voltage level to be encountered is possible in an active system. Thus connection of the board to an analog or a digital bus can occur when the system signals are in any of the states noted above.
A more specific approach to prevent turbulence from being generated on a bus line when a bus connected substrate, i.e. a pluggable unit, is inserted or extracted in a hot-line state of a computer system, is disclosed in Japanese patent publication No. JP 512 7777 entitled "Substrate Insertion and Extraction in Hot-Line State" which is assigned to Fujitsu Ltd. The substrate is equipped with a first connector and a second connector. Through the first connector the substrate is connected to the bus of a CPU and a power source, wherein the second connector serves to connect the substrate to an electric power supply. Further a switch is provided which is operated at the time of insertion or extraction of the substrate in the hot-line state, as well as an interruption initiating circuit which initiates an interruption to the CPU when the switch is operated and first and second attachment/detachment detecting circuits. The first of these circuits generates a first connector attachment/detachment signal when the first connector is connected; the second circuit generates a second connector attachment/detachment signal when the second connector is connected. In particular a bus driver control circuit is provided which holds a bus driver high in impedance with the aforementioned connector signals. Further, a write register which holds the permission for insertion or extraction of the CPU in the hot-line state and which generates an insertion/extraction permission signal, is provided. When the CPU issues the permission for insertion or extraction in hot-line states, bus access is stopped. Thus the subject matter of that patent publication also depends on holding and stopping the bus, and placing it in a high impedance state during live insertion. But there are no additional provisions for immunity to spurious disturbances. A switch is used to interrupt the CPU's operation analogous to the door as in U.S. Pat. No. 5,310,998 cited above.
Another approach where the bus is set to a high level is disclosed in Japanese patent publication No. JP 2094 271 entitled "Interface Package" which is assigned to NEC Corporation. In order to prevent an adverse effect on the bus it is particulary proposed to use connector pins with two kinds of lengths, and setting the bus output to an open high level. The upper pins and lower pins of an interface package (IP) are set to long pins; the intermediate pins are set to short pins. A specific pin of the long pins is assigned as power terminal, it is first brought into contact when the IP is inserted, and it is last separated when the IP is removed. The long pins are adapted for a power cut-off detecting integrated circuit (IC) and a buffer IC. When the IP is inserted, the detecting IC is operated as soon as the terminal is brought into contact with the IP, and the output of the buffer IC is set to an open high level. Therefore that invention allows the bus to flood to an open high level during the live insertion progress. The sequencing during live insertion is controlled with different staggered pin lengths versus a door as in U.S. Pat. No. 5,310,998 or a switch as in the JP 512 7777. Staggered pin length sequencing, however, is not at issue for the present invention.